library IEEE; use IEEE.std_logic_1164.all; use work.UPAC.all; entity STATE_GENERATOR is port ( CLK : in std_logic; RESET : in std_logic; STATEIN : in STATE; STATEOUT : out STATE); end STATE_GENERATOR; architecture RTL of STATE_GENERATOR is begin -- RTL process (CLK, RESET) begin -- process if RESET = '1' then -- asynchronous reset (active low) STATEOUT <= INIT; elsif CLK'event and CLK = '1' then -- rising clock edge STATEOUT <= STATEIN; end if; end process; end RTL;