library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; library UNISIM; use UNISIM.VComponents.all; entity SRAM_CONTROLLER is port ( -- external XWR : out std_logic; BWA : out std_logic_vector(3 downto 0); IO : inout std_logic_vector(31 downto 0); A : out std_logic_vector(19 downto 0); --IOP : inout std_logic_vector(3 downto 0); LBO : out std_logic; CEA2 : out std_logic; CEA2X : out std_logic; CELA1X : out std_logic; CEHA1X : out std_logic; CEN : out std_logic; ADVLD : out std_logic; ZZ : out std_logic; XOE : out std_logic; --internal CLK : in std_logic; RW : in std_logic; --read:1,write:0 ADDRESS : in std_logic_vector(19 downto 0); WRITEDATA : in std_logic_vector(31 downto 0); READDATA : out std_logic_vector(31 downto 0) ); end SRAM_CONTROLLER; architecture BEHAVIOR of SRAM_CONTROLLER is signal FLAG0 : std_logic; signal FLAG1 : std_logic; signal FLAG2 : std_logic; signal WRITE_BUFFER0 : std_logic_vector(31 downto 0); signal WRITE_BUFFER1 : std_logic_vector(31 downto 0); signal WRITE_BUFFER2 : std_logic_vector(31 downto 0); signal RESET : std_logic; begin -- BEHAVIOR XOE <= '0'; LBO <= '0'; BW <= "0000"; CELA1X <= '0'; CEHA1X <= '0'; CEA2 <= '1'; CEA2X <= '0'; ZZ <= '0'; XRW <= RW; CEN <= '0'; ADVLD <= '0'; IO <= WRITE_BUFFER2(31 downto 0) when (FLAG2 = '0') else (others => 'Z'); RC : ROC port map ( O => RESET); main : process (CLK, RESET) begin -- process main if RESET = '1' then FLAG0 <= '1'; FLAG1 <= '1'; FLAG2 <= '1'; WRITE_BUFFER0 <= (others => '0'); WRITE_BUFFER1 <= (others => '0'); WRITE_BUFFER2 <= (others => '0'); A <= (others => '0'); elsif CLK'event and CLK = '1' then READDATA <= IO; FLAG0 <= RW; FLAG1 <= FLAG0; FLAG2 <= FLAG1; WRITE_BUFFER0 <= WRITEDATA; WRITE_BUFFER1 <= WRITE_BUFFER0; WRITE_BUFFER2 <= WRITE_BUFFER1; A <= ADDRESS; end if; end process main; end BEHAVIOR;